1. Field of the Invention
The present invention relates to a Power Integrated Circuit ("PIC") structure, and to a manufacturing process thereof.
2. Discussion of the Related Art
The name "Power Integrated Circuit" ("PIC") refers to a monolithic integrated structure comprising a power stage and a driving, control and protection circuit.
Several efforts have been made to obtain PICs with a minimum increase in the fabrication process complexity. Examples are given in the documents listed below, each of which is incorporated herein by reference:
1) J. P. Mille, Proceedings of Symposium on HV & Smart Power ICs, Los Angeles, May 1989, pages 517-525, PA1 2) F. Goodenough, Electronic Design, Mar. 4, 1993, pages 27-28; PA1 3) S. L. Wong, M. J. Kim, J. C. Young and S. Mukherjee, Proceedings of 3rd ISPSD, Baltimore, April 1991, pages 51-55; PA1 4) F. H. Beherens, G. Charitat and P. Rossel, Proceedings of Symposium on Materials and Devices for Power Electronics, Florence, September 1991, pages 98-103.
In references 1) and 2) manufacturing processes are described for providing PICs with a Vertical Double-diffused power MOSFET ("VDMOSFET") and/or a power NPN bipolar junction transistor power stage, where the driving and control circuitry comprises N-channel MOSFETs (both enhancementand depletionmode); the N-channel MOSFETs of the driving and control circuitry are provided in a P type well diffused in the lightly doped N type epitaxial layer constituting, together with a heavily doped N+ silicon substrate, the VDMOSFET drain; the electric isolation of the driving and control circuitry from the power stage is achieved by reverse biasing the P type well/N type epitaxial layer junction (this technique is known as self-isolation).
With respect to the VDMOSFET manufacturing process, these processes only require the addition of a few steps, such as the definition of the P type well and of the depletion implant. A major drawback resides in that it is difficult to implement complex logic and analog functions with just N-channel MOSFETs.
References 3) and 4) describe how a conventional P-well CMOS process can be adapted to integrate a VDMOS-based PIC. The driving and control circuitry comprises both N-channel and P-channel MOSFETs, the N-channel MOSFETs being integrated inside a P type well diffused into a lightly doped N type epitaxial layer, grown over a heavily doped N+ substrate; the P-channel MOSFETs on the other hand are directly fabricated in the N type epitaxial layer, which also forms, together with the N+ substrate, the drain of the VDMOSFET.
Since the channel region of the P-channel MOSFETs coincides with the VDMOSFET drain, such a device cannot be used as a Low Side Driver ("LSD") (with the load connected between the power supply and the VDMOSFET switch): in this circuit configuration, in fact, the VDMOSFET drain potential varies from a few tenths of Volts up to the voltage supply (VCC). If the device is used as a High Side Driver ("HSD") (with the load connected between the VDMOSFET source and ground), the VDMOSFET drain is connected to the voltage supply: the P-channel MOSFETs must therefore have the source electrode connected to VCC.
In view of the state of the art just described, an object of the present invention is the integration of a PIC structure with driving and control circuitry comprising both N-channel and P-channel MOSFETs, that overcomes at least the above mentioned drawbacks.